1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device in which hot carrier resistance can be improved and silicide layer can be formed with high reliability.
2. Description of the Related Art
In recent years, a merged DRAM (Dynamic Random Access Memory)xe2x80x94logic LSI has been used in many cases. In the merged DRAM-logic LSI, a logic integrated circuit and a DRAM are simultaneously formed on a single chip, to make a performance of a ULSI (Ultra Large Scale Integration) higher and make a function thereof higher. This merged DRAM-logic LSI is expected to include a large capacity of DRAM without drop of the performance of logic parts. It is also expected that the merged DRASM-logic LSI can be manufactured at a low cost.
For this reason, the structure in which silicide layer is formed on the surface of high impurity concentration diffusion layer serving as a source/drain of a MOSFET is used to achieve the high performance, in the merged DRAM-logic LSI. Silicon nitride film is often used as a spacer for covering a side portion of a gate electrode to form this silicide layer in self-alignment,
On one hand, in a general purpose DRAM, the silicide layer is not formed on the surface of the diffusion layer, in view of a cost. On the contrary, if the DRAM is merged with the logic LSI, the silicide layer can be formed on the surface of the diffusion layer of the MOSFET (Metal Oxide Silicon Field Effect Transistor) of the DRAM without increasing the cost.
However, the diffusion layer used as the source/drain of the MOSFET in a DRAM memory cell is the diffusion layer having a low impurity concentration of which a junction depth is shallow. Here, the reason why the source/drain of the MOSFET in the DRAM memory cell is formed as the diffusion layer having the low impurity concentration of which the junction depth is shallow is to suppress a short channel effect, suppress a junction leak current and improve a hot carrier resistance. Moreover, silicon oxide film is used as an insulating film spacer formed on the side portion of the gate electrode of the MOSFET.
However, the following first to third problems are incurred if the silicide layer is formed on the surface of the diffusion layer having the low impurity concentration of which the junction depth is shallow as the source/drain of the MOSFET in the DRAM memory cell.
Firstly, a contact resistance is high between the silicide layer and the diffusion layer having the low impurity concentration. Although the silicide layer is formed on the region of the source/drain, there may be a case in which an external resistance in the region of the source/drain is high, conversely to the original object.
Secondly, the shallow depth of the diffusion layer of the source/drain causes the junction leak current to be increased. Thirdly, the use of the silicon nitride film as the insulating film spacer on the side portion of the gate electrode causes the hot carrier resistance to be deteriorated.
A method of selectively forming a silicide layer on a diffusion layer in a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 3-205865), as a method of avoiding a part of the above-mentioned problems. The gazette discloses a method that a silicide layer is formed on a surface of the diffusion layer in a first MOSFET of a semiconductor device and a silicide layer is not formed on a surface of the diffusion layer in a second MOSFET of the semiconductor device.
The conventional example noted in the gazette will be described below with reference to FIGS. 1 to 5.
At first, an N-type well 102, a field oxide film 103, a gate oxide film 104, a gate electrode 105 formed of polysilicon and the like, a P-type low impurity concentration region 107 and side walls 106 are formed on the surface of a semiconductor substrate 101, in FIG. 1.
Next, as shown in FIG. 2, a silicon nitride film 112 serving as a first insulating film is grown on an entire portion of the surface. The silicon nitride film 112 has a function of a mask to divide the source/drain between the region on which a silicide layer is formed and the region on which a silicide layer is not formed. The silicon nitride film 112 has a thickness of, for example, about 30 nm. Then, a silicon oxide film 113 serving as a second insulating film is deposited on the entire portion of the surface in a thickness of about 100 nm.
Next, as shown in FIG. 3, photolithography technique is used to etch the silicon oxide film 113 corresponding to the region on which the silicide layer is formed. After that, the silicon nitride film 112 corresponding to the same region is etched.
Next, as shown in FIG. 4, a metal having a high melting point, for example, Ti is sputtered on the entire surface in about 80 nm. Then, annealing is performed thereon so that Ti and Si react to together in the region, in which the silicon oxide film 113 is removed, to accordingly form a Ti silicide 109. The Ti silicide 109 has a thickness of, for example, about 100 nm.
Next, as shown in FIG. 5, the Ti that is not constitutes the Ti silicide 109 and is present on the region where the silicon oxide film 113 is not removed, is removed by the etching. Then, a silicon oxide film 114 with a thickness of about 25 nm is formed on the entire surface. After that, a P-type high concentration impurity region 111a is formed by, for example, ion implantation of boron.
However, in the conventional example, it is necessary to increase a lithography process to form the region where the Ti silicide 109 is formed and the region where it is not formed. Thus, the conventional example has the defect of increasing the manufacturing process.
Moreover, in the conventional example, the same material is used in the region where the silicide layer is formed and the region where it is not formed, for the side wall of the gate electrode of the MOSFET. Thus, the simple application of the conventional example to the merged DRAM-logic device results in the problem that the hot carrier resistance of the MOSFET is deteriorated.
To change the material of the side wall in the region where the Ti silicide, 109, is formed, the once-formed side wall 106 is removed by using the lithography process. After that, a next side wall 106 can be formed newly. However, in order to carry out this treatment, it is necessary to increase one or more lithography processes. Thus, this has the defect of increasing the manufacturing process.
Japanese Laid Open Patent Application (JP-A-Heisei 9-116113) discloses a method of manufacturing a semiconductor device, as described below. A memory cell is formed after a circuit field effect transistor is covered with insulating film. After the formation of the memory cell, the surface of diffusion layer of the circuit field effect transistor is exposed to then form the covered conductive layer on the exposed surface of the diffusion layer.
Japanese Laid Open Patent Application (JP-A-Heisei 4-262573) discloses a method of manufacturing a semiconductor device, as described below. A first side wall protection film that is common to a memory cell array formation region and a peripheral circuit formation region is formed when forming a transistor having LDD structure. After that, anisotropy etching is further performed on only the first side wall protection film in the peripheral circuit formation region to thereby form a second side wall protection film having a width narrower than that of the first side wall protection film. Then, LDD regions having different widths are formed in the respective memory cell array region and peripheral circuit region, with these first and second side wall protection films as respective masks.
Japanese Laid Open Patent Application (JP-A-Heisei 10-41480) discloses a method of manufacturing a semiconductor memory device, as described below. A cell array region, a core region and a peripheral circuit region are respectively formed in a semiconductor memory device having transistor structure. A source/drain of a transistor in the cell array region is provided with low concentration impurity regions. A source/drain of a transistor in the core region is provided with a high concentration impurity region 112 and a low concentration impurity region 108 that are formed with the same dopant. A source/drain of a transistor in the peripheral circuit region is provided with a high concentration impurity region and a low concentration impurity region that are formed with dopants different from each other. Especially, the dopant of the low concentration impurity region of the transistor in the core region is lower in diffusion degree than the dopant of the low concentration impurity region of the transistor in the peripheral circuit region.
The present invention is accomplished in view of the above-mentioned background. Therefore, the present invention provides a semiconductor device in which the hot carrier resistance is not deteriorated without the increase of the manufacturing process, and a method of manufacturing it.
Moreover, the present invention provides a semiconductor device in which the silicide layer can be formed with high reliability without the deterioration of the hot carrier resistance and the increase of the manufacturing process, and a method of manufacturing it.
The present invention has been made to solve the above-described problems of the conventional semiconductor device and method of manufacturing it. An object of the present invention is to provide a semiconductor device and method of manufacturing it to provide a semiconductor device and method of manufacturing it in which hot carrier resistance can be improved. Another object is to provide a semiconductor device and method of manufacturing it in which silicide layer can be formed with high reliability.
In order to achieve an aspect of the present invention, a method of manufacturing a semiconductor device includes (a) providing a semiconductor substrate having first and second semiconductor element formation regions, (b) forming a second gate electrode of a second semiconductor element in the second semiconductor element formation region in a state that the first semiconductor element formation region is masked, (c) forming a second source/drain region of the second semiconductor element in the second semiconductor element formation region in the state that the first semiconductor element formation region is masked, (d) forming second side wall insulating films on side portions of the second gate electrode in the state that the first semiconductor element formation region is masked, (e) forming a first gate electrode of a first semiconductor element in the first semiconductor element formation region in a state that the second semiconductor element formation region is masked, (f) forming a first source/drain region of the first semiconductor element in the first semiconductor element formation region in the state that the second semiconductor element formation region is masked, and (g) forming first side wall insulating films on side portions of the first gate electrode.
In this case, the steps (e), (f) and (g) are performed after the steps (b), (c) and (d) are performed.
Also in this case, the steps (b), (c) and (d) are performed after the steps (e), (f) and (g) are performed.
Further the method of manufacturing a semiconductor device further includes setting an impurity concentration of the first source/drain region to a predetermined impurity concentration.
In order to achieve another aspect of the present invention, the method of manufacturing a semiconductor device further includes forming a silicide layer on the first source/drain region set to the predetermined impurity concentration.
In this case, the first semiconductor element is a MOSFET of a logic integrated circuit, and the second semiconductor element, is a MOSFET of a memory cell of a DRAM.
Also in this case, the forming the silicide layer includes forming the silicide layer in self-alignment with the first side wall insulating films.
Further in this case, the first and second side wall insulating films are formed of materials different from each other.
In this case, the second side wall insulating films are formed of silicon oxide.
Also in this case, the first side wall insulating films are formed of silicon nitride.
Further in this case, masks for masking the first and second semiconductor element formation regions are different from each other.
In this case, the forming a first side wall insulating films includes forming the first side wall insulating films in the state that the second semiconductor element formation region is masked.
Also in this case, the first source/drain region set to the predetermined impurity concentration is higher in impurity concentration than the second source/drain region.
Further in this case, the second source/drain region is connected to one of an electrode of a capacitor of a memory cell of a DRAM and a bit line of the memory cell of the DRAM.
In this case, the second source/drain region set to the predetermined impurity concentration is connected to a bit line of a memory cell of a DRAM.
Also in this case, a plurality of the second gate electrodes are formed in the second semiconductor element formation region in the step (b), and the step (b) includes masking the first semiconductor element formation region and an element separation region provided between the first and second semiconductor element formation regions.
Further in this case, the method of manufacturing a semiconductor device further includes forming a dummy gate electrode for covering the second source/drain region when an impurity concentration of the first source/drain region to the predetermined impurity concentration is set.
In this case, the forming a dummy gate electrode includes forming a dummy gate electrode such that a third side wall insulating film is formed on a side portion on a side of the first semiconductor element formation region of the dummy gate electrode and a fourth side wall insulating film is formed on a side portion on a side of the second semiconductor element formation region of the dummy gate electrode.
Also in this case, the forming a dummy gate electrode includes forming a dummy gate electrode by using a first mask to mask the first semiconductor element formation region when the second gate electrode is formed and a second mask to mask the second semiconductor element formation region when the first gate electrode is formed.
In order to achieve still another aspect of the present invention, a semiconductor device includes a semiconductor substrate in which first and second semiconductor element formation regions electrically separated from each other are formed, a first MOS transistor formed in the first semiconductor element formation region, a first insulating film spacer formed on a side portion of a gate electrode of the first MOS transistor, a second MOS transistor formed in the second semiconductor element formation region, and a second insulating film spacer which is formed on a side portion of a gate electrode of the second MOS transistor and is formed of material different from that of the first insulating film spacer.
In this case, the first insulating film spacer has a function of improving a hot carrier resistance of the first MOS transistor, and the second insulating film spacer has functions of protecting a gate electrode of the second MOS transistor and helping to form a silicide layer when the silicide layer in self-alignment in a source/drain region of the second MOS transistor is formed.
In order to achieve yet still another aspect of the present invention, the semiconductor device further includes a dummy gate electrode which is formed between the first and second semiconductor element formation regions and has a gate electrode structure of a MOS transistor, a third insulating film spacer formed on a side portion on a side of the first semiconductor element formation region of the dummy gate electrode, and a fourth insulating film spacer formed on a side portion on a side of the second semiconductor element formation region of the dummy gate electrode.
The present invention provides a method of manufacturing a semiconductor device, in which the material (for example, silicon oxide film) of an insulating film spacer formed on a side portion of a transistor of a DRAM memory cell and the material (for example, silicon nitride film) of an insulating film spacer formed on a side portion of a transistor other than the memory cell are different from each other, when forming a semiconductor integrated circuit in which a DRAM and a logic circuit are merged on a single chip.
As shown in FIGS. 7 to 13, respective gate electrodes of MOSFETs in a memory cell and a peripheral circuit region are sequentially formed with different masks. Accordingly, the materials of the insulating film spacers formed on the side portions of the gate electrodes can be made different from each other without the increase of the total number of masks.